a) Field of the Invention
The present invention relates to a semiconductor device including an integrated circuit (IC) chip, and more particularly to a semiconductor device having a coated insulation film constituting an interlevel insulation film of an IC chip.
b) Description of the Related Art
As a conventional protective structure for an IC chip, a seal ring structure such as shown in FIGS. 3 and 4 is Known.
Referring to FIG. 4, a plurality of chip inner regions 30A, 30B are formed on the surface of a semiconductor wafer 10. Each chip inner region has an IC constituted by a number of circuit elements and multi-layer wirings. The periphery of each chip inner region is provided with a seal ring structure shown in FIG. 3 so as to prevent external water contents and impurities from invading into the chip inner region.
The seal ring structure is generally formed at the interface between a scribing region 32A(32B) where the silicon surface is exposed and the chip inner region 30A(30B) where a field insulation film 12 is formed. A first interlevel insulation film 14 covering the ends of the field insulation film 12 formed on the substrate surface and surrounding the chip inner region 30A, a first level wiring (seal ring) layer 16, a second interlevel insulation film 18, a second level wiring layer (seal ring) 20, and a passivation insulation film 22, are formed in this order from the bottom. The passivation insulation film 22 is commonly made of a silicon nitride film formed by plasma chemical vapor deposition (CVD)
As shown in FIG. 4, a wafer substrate 10 including each chip inner region 30A, 30B and its peripheral seal ring region is diced along crossed scribing regions 32A, 32B to form separate IC chips. The wafer 10 may be severed at any area within the scribing region 32.
With the conventional seal ring structure, as shown in FIG. 4, a notch X reaching the chip inner region 30A is formed sometimes when dicing the wafer. FIG. 5 shows an IC chip 30 in which such a notch X exposes the ends of the insulation films 12, 14, and 18 at the chip periphery 30E. Like components to those shown in FIG. 3 are represented by identical reference numerals.
Referring to FIG. 5, a p-type well region 10W is formed on the surface of an n-type semiconductor substrate 10. MOS transistors Ta, Tb of a lightly doped drain (LDD) structure are formed on the surface of the well region 10W within moats surrounded by the field insulation film 12. The region 30a in which IC elements such as transistors Ta, Tb are formed is called an element region.
The first interlevel insulation film 14 is interposed between gate electrode layers 13G of transistors Ta, Tb and first level wiring layers 16S, 16D, and made of, for example, boron phosphorus silicate glass (BPSG). The first level wiring layers 16S and 16D are used as source and drain wirings.
The second interlevel insulation film 18 is interposed between first level wiring layers 16S, 16D and second level wiring layers 20D. The second interlevel insulation film 18 is formed, for example, by a flat spin-on-glass (SOG) film 18b and a pair of silicon oxide films 18a and 18c sandwiching the SOG film 18b. The wiring layer 20D is connected through a via hole 18P formed in the insulation film 18 to the wiring layer 16D, and used as the drain wiring.
If the SOG film 18 is exposed at the chip periphery 30E, external water contents (H.sub.2 O) invades sometimes into the chip inner region via the SOG film 18b. If an organic SOG film is used as the SOG film, a possibility of invasion of water contents becomes very high. Invaded water contents rapidly diffuse in the SOG film 18b and reach the element region 30a. Water contents diffused in the SOG film 18b gradually diffuse downward so that fixed positive charges are generated in the field insulation film 12. As a result, the conductivity type of the surface of the p-type well region 10W is inverted to an n-type, allowing a leak current I.sub.L to flow, for example, between the transistors Ta and Tb and hindering a normal transistor operation.
Water contents diffused in the SOG film 18b also reach the wiring layers 16S, 16D, 20D made of, for example, Al or Al alloy. These wiring layers are sometimes corroded, lowering the reliability thereof.
In order to solve the above problems, the widths (generally in the order of 100 .mu.m) of the scribing regions 32A, 32B may be widened. However, this approach reduces the number of chips obtainable from one wafer, and is not a practical solution.